John,

It is the newest batch I believe, '02a'.

Thanks

On Sunday, June 8, 2014 7:58:45 PM UTC-4, Thomas Owen wrote:
>
> All,
> I had posted this to the thread dealing with ordering this card, but 
> decided to post a new topic dealing with the problem I have had with final 
> checkout of the board.
>
> During assembly the board passed all the 'in progress' checks.  The final 
> steps were to output to different ports:
>
>
> I have output the following and everything passes:
>
> QO33,80 ; Configures ports A, B and C as output ports
> QO32,2B ; Selects right hand pair of digits
> QO30,01; display 01on right digit pair and work through each bit - all ok
>
> QO32,2c; Selects middle pair of digits
> QO30,01; Should display 01 on middle digit pair, work through each bit - 
> all ok
>
> QO32,2d; Selects left hand pair of digits
> QO31,01; Should display 01 on left digit pair, work through each bit - all 
> ok
>
> All displays are correct.
>
> Now the final step is the Drive Select and that is where I am having 
> trouble:
>
> Board always comes up with 'Drive A' selected
>
> Now,  QO34,0; no change
>
> Reset, start again:
>
> QO34,1; no change
>
> I can never select drive B.   
>
> Several generous members (thank you David Fry) have made suggestions, and 
> here is where I now stand:
>
> My preliminary check this afternoon shows me that there is a timing issue 
> at U15, the 74ls02.  Using my logic analyzer and monitoring the inputs and 
> the output (which clocks the drive select flip flop) I see a big timing 
> difference between SEL_SECOND and WR.
>
> What this means is that the output of the gate never goes high allowing 
> the bit change to effect drive change/selection.
>
> I am going to get some screen shots from the analyzer tomorrow, and if 
> anyone has any suggestions I would greatly appreciate it.
>
> Thanks,
> Thomas
>
>

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