Thanks Pete -- my design uses the SMT versions of the transistors so I'm particularly interested in reducing the power dissipation. Please clarify the placement of the "helper" resistor -- in the vertical leg of the Q1 collector circuit, or in the horizontal leg of the Q2 base connection? If I understand the circuit right, it's the vertical leg. Terry
On Friday, February 27, 2015 at 2:44:51 AM UTC-6, petehand wrote: > With the conventional circuit, you have two saturated transistor switches, > each of which needs to turn off to blank the anode. Each may take a few > microseconds, and the second stage doesn't start its time delay until the > first stage turn off is completely finished. With most designs the > transistors are over-driven, which makes the delays worse. Switch-on time > of the next stage is not delayed, so you can easily get more than 10 > microseconds overlap with the next anode. > > The cascode stage has essentially zero switching time, and with a bit of > attention to base current and resistor values you can cut the switching > time of the PNP to a minimum, so even if there is a slight overlap it's > likely to be less than the ionization time of the next tube. I don't claim > that this circuit will always eliminate ghosting entirely, but I do assert > that I've made half a dozen multiplexed clocks using a similar circuit to > this (I use a 2ms digit period), switching the anodes simultaneously with > the digit cathodes, and I've never had any ghosting. > > My example 1mA current to turn on Q2 is ridiculously high, by the way. > Experiment with the R2 emitter resistor - it should work with 100k. But as > you increase R2, make R1 an equal value, otherwise Q2 won't turn on. > > On Thursday, February 26, 2015 at 5:46:52 AM UTC-8, Terry S wrote: >> >> Pete, that's a nice application for the cascode circuit... Help me >> understand how it eliminates concerns about dead time and ghosting. >> >> Terry >> >> >> On Thursday, February 26, 2015 at 3:05:55 AM UTC-6, petehand wrote: >> >>> >>> <https://lh5.googleusercontent.com/-_PML27wwc9w/VO7hHsuYRwI/AAAAAAAAATA/LVcwCOp5mWw/s1600/IN17.jpg> >>> I did mean to change R22 to 10k, but I can suggest an even better way. >>> This is a circuit I've used to multiplex IN17s, with no dead period and no >>> ghosting. It looks terrifyingly unsafe. Let me explain. >>> >>> When the processor pin is high, Q1 base-emitter voltage is 0 and the >>> transistor is cut off. The port pin sees no high voltage. When the port pin >>> goes low the transistor turns on as a constant current source, the current >>> set by (5 - 0.6)V/R2 or about 1mA. This drops 170V across Q1 and 10V across >>> R1, which turns on Q2. Q1 is operating in linear mode, not saturated, so it >>> switches in nanoseconds. Resistor R1 is necessary to help Q2 to switch off >>> rapidly. >>> >>> This configuration of Q1 with the implied transistor inside the MPU is >>> called a cascode <http://en.wikipedia.org/wiki/Cascode>. >>> >>> >>> >>> >>> On Wednesday, February 25, 2015 at 3:45:43 AM UTC-8, joenixie wrote: >>>> >>>> Hmmm... interesting observation Pete, are you talking about changing >>>> R21 or R22 to 10K? I chose 100K because I have them in my NixieNeon clock. >>>> >>>> -joe >>>> >>>> -- You received this message because you are subscribed to the Google Groups "neonixie-l" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/neonixie-l/70f90290-d323-4220-bf10-3687a724741b%40googlegroups.com. For more options, visit https://groups.google.com/d/optout.
