On Wednesday 02 February 2005 13:39, Timothy Miller wrote:
Daniel Phillips wrote:
On Wednesday 02 February 2005 10:05, Timothy Miller wrote:
There will be a single DMA engine. What matters is how addresses are computed and where the data is sent. There's not a whole lot to it.
Don't you want command DMA and texture DMA to be able to run in parallel?
How would you do that? You only have one bus.
You've only got one processor and processes run in parallel. One possibility is that, when texture DMA begins, command DMA stops and command DMA resumes when texture DMA completes.
We're talking past each other here.
There's one single DMA engine. It has a ring buffer control and a queue for indirect requests. The indirect queue has priority over ring buffer. It processes requests in the order it receives them. Requests amount to an address, length, and internal target.
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