On Thu, 24 Feb 2005 18:22:28 -0500, Daniel Phillips <[EMAIL PROTECTED]> wrote: > > Here are a few random thoughts on cache design... Each cache element has > to be tagged, probably with a 23 bit address. Each cache element has > to be able to compare against the requested address. A cache line is > 32 bits, probably. I think we need at least 16 entries to get any > measurable improvement from it. Timothy has suggested that each memory > controller will have its own cache, and I can see how that simplifies > things, but on the other hand it will require more cache entries in > total to get the same benefit versus a shared cache.
I was thinking four entries, more precisely two pixel pairs. :) _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
