Am Samstag, den 28.05.2005, 12:49 -0400 schrieb Timothy Miller: > > Now for the math. Timothy said to expect a 20 clock delay for random > > access to card memory. I'm going to assume that is 20 clocks in the > > 200Mhz domain. > > No. I'm assuming a large part of that delay comes from synchronizing > FIFOs between clock domains.
Why does the VGA controller have to run at a different clock rate than the memory controller? > Furthermore, I'm assuming a row miss in > the memory controller, and numberous other delays. Can the VGA controller get a more direct access to the cache and/or VRAM? Direct enough to be able to predict when the results of a read arrive? - Viktor Pracht _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
