On 5/30/05, Eric Smith <[EMAIL PROTECTED]> wrote: > Timothy wrote: > > For the architecture we're fiddling with, it is necessary. 512x36 > > bits of memory in random logic is HUGE. We're using a block RAM. > > Sure. But isn't that program memory? I thought the register file > only needed a fairly small number of registers, based on Patrick's > example code.
Yes, but we had this clever idea of unifying the two. This way, there's no need for a special instruction for full-size immediate constants, for instance. (But just because it's cute doesn't mean it's a good idea.) > > > Ok, so we'd be able have more overlap in the > > pipeline, but not THAT much. I wish I could draw a diagram here, but > > if you fully pipeline the processor, then you end up having to be able > > to make potentially 8 reads and 2 writes to the register file all at > > the same time. > > Why does the nanocontroller need 8 reads and 2 writes to a single > block of memory??? When does a single instruction write to two > locations? I thought the nanocontroller was just a simple processor > that is supposed to emulate some of the VGA capabilities! Any given instruction can do two reads at the same time, followed by a write. Include instruction fetch. Overlap that with four other instructons also in the pipeline, and that's a lot of memory activity. > > Is needing ten register file ports the reason it was expected to take > a minimum of five cycles per instruction? Sortof. There's one cycle with no register access, where the ALU does its job. > > Anyhow, if that's really necessary, just do it in two consecutive > cycles with a five-port RAM that has four read ports and one write > port. Now you're up to 32 CLBs for the total register file, but that's > still only 1% of the 3S1500 or 0.5% of the 3S4000. As you start adding ports, you might as well just use random logic, which is one bit per CLB. > > I want to see more of this. Mind educating me? One challenge that I > > have had with processor designs is the restriction that I could do one > > read and one read or write per cycle with a dual-ported RAM. > > You can build n-read 1-write register files by duplicating a 2-port > register file n times, with the write port shared by all the RAMs. Doesn't sound very economical. Also, you're doing this for performance... do we really need the performance? > Unfortunately the trick doesn't work for 2 write ports; you'd need a > triple-ported RAM to do that. > > > I want to see this. :) > > If you're talking about my aeMB suggestion, the code is > on opencores. > > Eric > > _______________________________________________ > Open-graphics mailing list > [email protected] > http://lists.duskglow.com/mailman/listinfo/open-graphics > List service provided by Duskglow Consulting, LLC (www.duskglow.com) > _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
