On Tue, 2005-05-31 at 09:26 -0400, Timothy Miller wrote: > What are your pipeline stages? I'm thinking there's: > - fetch > - read > - compute > - write
I assume he's referring to a classic 5-stage design with a MEM stage: -fetch -decode -execute -memory access -register writeback -Chip _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
