While it seems to work so far, It's certainly not complete. What I've checked into the repository exists only to let us simulate the PCI core. There are other things that need to be added to the design, and, of course, tests have to be written on those.
What you need to simulate it for yourself: iverilog gtkwave With Gentoo, I just did "emerge iverilog gtkwave". Other distros will have to get it another way, and users of those distros should feel free to explain how. The included 'runsim' script will compile the verilog, run it, and bring up the signal viewer. If you tell gtkwave to "file > open traces" and give it test2.traces, you'll see some of the important signals involved in this test. Get the source code from: svn co https://svn.suug.ch/repos/opengraphics/main/trunk/pci All the test does so far is write a base address register, read it back, and then write it with something else, a normal part of initializing a PCI device. That much seems to work. Things I could use help with: (1) Simulating other sorts of transactions, like memory reads and writes (2) Finishing other parts of what goes into the Lattice chip, like the PROM interface Although many of you have stayed away from this because you don't have access to a PCI spec, there are other parts of the design that are not part of that. I would like for the community to help push forward on that. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
