Hello,
I've subscribed to the mailing list a week ago. I'm a French FPGA/ASIC
design engineer and I have some experience in PCI/PCI-X protocols,
verilog, vhdl.
I've already designed PCI and PCI-X interfaces using the Xilinx
Logicore IP and I would like to get involved in this project.
I've retrieved the subversion database. I do have some questions however...
1. What should I read for specifications? Is there an architecture
already done for the fpga?
2. There is not much verilog in the database. Does that represent the
current status of the project?
3. Is there an #IRC channel?
A plus tard.
Sebastien
--
--Seb
http://tetsuo3.free.fr/
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