On 12/5/05, Attila Kinali <[EMAIL PROTECTED]> wrote: > On Mon, 5 Dec 2005 08:29:42 -0500 > Timothy Miller <[EMAIL PROTECTED]> wrote: > > > On 12/5/05, Attila Kinali <[EMAIL PROTECTED]> wrote: > > > Hm? How does the plans for the ASIC differ from the plans for the FPGA? > > > > The ASIC is more cost-sensitive, so we may have to leave some things out. > > Interesting. I thought that the mask costs are so high, that > it wouldnt matter to have more functionality on the chip and a > bit more of peripherial stuff.
Die area is a factor, but it's more than that. The more you pack in there, the more that can fail, and the lower your yield. Plus, we're not going for full custom. The sorts of chips we'd be going after already have the silicon doped and some metal, and our circuitry is added by more layers of metal. Lower performance, lower cost, fewer masks. The dies come in fixed sizes, and if some low-priority feature pushes over from one size up to the next, we'll drop it in favor of the smaller die. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
