On Fri, 13 Jan 2006 02:02, Timothy Miller wrote:
> On 1/11/06, Richard Smith <[EMAIL PROTECTED]> wrote:
> > If someone would write some good software that would generate lots of
> > different test patterns and modes I bet you could sell quite a few as
> > test pattern generators.  Especially with open source code that an OEM
> > could customize into their test setup.
>
> Mind if I steal your idea?  :)

Actually, what you could do is take some good fractals program with source - 
fractint comes to mind - and use that.   Zooms, interrupted fills followed by 
switching to a completely different fractal, etc.  It should give the 
hardware a good hard solid workout.

Wesley Parish
>
> > I know Bitworks could use at least one for generating various HD modes
> > or modes to fit some of the widescreen LCD panels.
> >
> > What will be the minimum dot clock you can generate?
>
> Actually, I don't know.  PLLs usually have a limited range.  For
> instance, one we used on a Tech Source card couldn't go below 33MHz.
> Since we needed a lower rate for one particular mode, we added logic
> to divide it down further.  We always use Xilinx DCM's to deal with
> clock phasing, so we can just add logic to allow various
> multiplier/divisor ratios for the in-coming clock beyond the control
> we have over the external PLL.
>
> There's one thing that we needed done that never happened.  We're
> using the Lattice XP10 for the host interface on OGD (because it's
> flash programmable).  It has PLLs in it, but we don't know how good
> they are (statistically, any given PLL is probably going to suck).  We
> haven't been able to test it ourselves, and no one in the community
> has volunteered to do it for us.  I think Howard's just opted to use
> an external PLL that we know is good.  It's one we've used for ATC
> systems, so the jitter is very low.
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-- 
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-----
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