On Thu, 2 Mar 2006 15:13:26 +0000
Peter Brett <[EMAIL PROTECTED]> wrote:
> > I'd like to say, tho', that the schematics are probably not going to yield
> > any "bugs" - the errors that you will face will not come from schematic
> > problems but rather SI, PDS and stackup. These things are only evident
> > using a) high-power 2D field solvers (I still haven't worked out to do
> > this) b) trial & error c) US$250 / hour SI experts ;)
This is less about errors in the schematic but about
design errors.
Attila Kinali
--
wer soviel schoggi isst, kann sowieso nicht dumm sein ;-)
-- Sandra
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