Timothy Baldridge wrote:
So what benifits are you going to have in using CISC over RISC?
Smaller code sizes I guess, at the the expense of complexity.
In general... correct. But you can also do stuff like out-of-order
execution to work around some dependencies, or add hardware
multi-threading to enable multiple "simultaneous" rendering jobs. If
the pipeline for one thread stalls, you can fill the pipeline with work
from another thread.
I'm thinking for a GPU wider is going to be better than deeper. With
FPGAs were are going to be limited by the clock. Why make it worse by
going to CISC that relys on higher clock speeds? Why not make a simple
core so that we can pack 16-24 of them in one FPGA instead of one that
will take up half the CPU?
I would certainly like to see such a beast, it would be very
interesting. But ultimately I think deeper _and_ wider is the way to go ;)
Jeff
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