On 4/15/06, Lourens Veen <[EMAIL PROTECTED]> wrote: > > Can't we combine this with Timothy's MISC idea? Have a "CPU" with > load/move/store, and a bunch of functional units that can each perform > a complex (think Altivec/3DNow!/SSE3 or even more complex than that, > like a dot product) instruction. Newer processors can simply have more > functional units, and could be backwards compatible with their > predecessors. >
The idea I keep thinking about is to have a pipeline of general functional units. As a fragment passes down the pipeline, it's like executing instructions. If the number of instructions to be executed exceeds the pipeline length, the fragment gets forwarded back up to the beginning. Loops would get unrolled to the pipeline length; longer ones would work via the forwarding mechanism. Any sequence of instructions shorter than the pipeline length would get padded with NOOPs. The problem is that any more than a few general purpose registers would make every pipeline stage a massive amount of logic, limiting the number of stages. But the idea is to get great throughput at a low clock rate. We cannot design something to run at 500MHz. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
