On 6/21/06, Hamish <[EMAIL PROTECTED]> wrote:
> always @(posedge clock) begin
> if (drawing_line) begin
> ... next step in drawing line ...
> if (... last pixel ...) begin
> drawing_line <= 0;
> end
> end else if (start_line) begin
> ... grab input parameters into registers and start counter ...
> drawing_line <= 1;
> end
> end
How do you reset start_line? If I try to set it, iverilog complains that it's
a wire & not a reg... And if I don't set it, isn't the line going to start
drawing again as soon as drawing_line is reset?
start_line would be controlled by external logic. It's an input to
this block that does Bres.
Typically, we'd have some sort of busy output. When seeing that busy
is not asserted, external logic could pulse start_line for one clock
cycle. There are ways to save a cycle, but we'll get to those later.
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