On 6/21/06, Hamish <[EMAIL PROTECTED]> wrote:
On Wednesday 21 June 2006 18:20, Hamish wrote:
> On Wednesday 21 June 2006 02:15, you wrote:
> > > Part 1. The start of the line, always @(posedge bresLineStart) that
> > > calculates the delta's, whether it's steep, and the current point.
> > > Lastly it resets the output (bresLineEnded).
> >
> > It's good that you're doing this, because it reminds me to mention in
> > lesson 4 to never use something that isn't a clock net as a clock. :)
> >
> > You'll want to do something like this:
> >
> > always @(posedge clock) begin
> > if (drawing_line) begin
> > ... next step in drawing line ...
> > if (... last pixel ...) begin
> > drawing_line <= 0;
> > end
> > end else if (start_line) begin
> > ... grab input parameters into registers and start counter ...
> > drawing_line <= 1;
> > end
> > end
[deleted]
OK... Third try...
I have always @() on the Clock. Input of startline (signal) plus the line
endpoints... The output is to signal that the line drawing is done. (Or not
busy, depending on how you look at it).
There is a single always now. WIth a test for start of line or drawing.
Drawing state is set by the start of line. The stae diagram is thus
Idle <----------
| |
(Start a line) |
| |
Start Line |
| |
-> Drawing ----(finished)
| |
-------
Yes, that's the idea.
(Missing out the various signals sorry. Apologies for the crap ASCII art :)
//
// Draw a line using Bresenhams algorithm...
module bresLine(Clock, startBresLine, x0, x1, y0, y1, bresLineDone);
input Clock;
input startBresLine;
input [31:0]x0;
input [31:0]x1;
input [31:0]y0;
input [31:0]y1;
output bresLineDone;
reg bresLineDone;
reg bresLineDrawing=0;
You really don't want to be doing initializations like this for synthesis.
What you need is a global reset, and you do it like this:
always @(posedge clock) begin
if (reset) begin
bresLineDone <= 1;
bresLineDrawing <= 0;
... all regs you'll be assigning to ...
end else begin
.... logic ....
end
end
integer diffX=0;
integer diffY=0;
reg steep=0;
reg [31:0] startX=0;
reg [31:0] startY=0;
reg [31:0] endX=0;
reg [31:0] endY=0;
integer deltaX;
integer deltaY;
integer error=0;
integer yStep=0;
integer pointX=0;
integer pointY=0;
function [31:0] abs;
input [31:0] value;
begin
abs = value&'hefffffff;
end
endfunction
That won't give you abs.
First of all, although the synthesizer might be smart enough to figure
it out, [30:0] is likely to produce less logic than &'h7ffffff.
Secondly, what you have with this is the 2's compliment of the lower
31 bits, which is not the same as the absolute value.
task renderPixel;
input [31:0] pointX;
input [31:0] pointY;
begin
$display("pixel : (%x %x)", pointX, pointY);
end
endtask
always @(posedge Clock) begin
if(bresLineDrawing)
begin
$display(" : (%x %x)", pointX, pointY);
if(steep)
begin
renderPixel(pointY, pointX);
end
else
begin
renderPixel(pointX, pointY);
end
error=error+deltaY;
if((error<<1) >= deltaX)
begin
pointY=pointY+yStep;
error=error-deltaX;
end
// if(pointX<endX)
// begin
pointX=pointX+1;
// end
assign bresLineDone=(pointX>=endX);
This is good code, although you can't use 'assign' in an always block.
end
else
begin
if(startBresLine)
begin
// assign bresLineDone=1;
bresLineDone <= 0;
// Need the diff in x & y
diffX = x1-x0;
diffY = y1-y0;
steep = abs(diffY)>abs(diffX); // Line is steep (>45deg) if dY > dX
$display("bresLine: steep %x (%x %x %x %x)", steep, x0, x1, y0, y1);
// If it's a steep line, swap X & Y so we're drawing a shallow line
if(steep==0)
begin
startX=y0;
startY=x0;
endX=y1;
Missing endY here??
end
else
begin
startX=x0;
startY=y0;
endX=x1;
endY=y1;
end
deltaX=endX-startX;
deltaY=abs(endY-startY);
if(startY<endY)
begin
yStep=1;
end else
begin
yStep=-1;
end
pointY=startY;
pointX=startX;
end
end
end
endmodule
You are ambitous to do this before lesson 4 (which I hope to do tomorrow). :)
I haven't checked everything in perfect detail, but this is quite
excellent work here.
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