Timothy Miller wrote:
The objective is to download ISE web pack 6.3 (classic), along with
the service pack, and make sure it still supports the 3S4000. First,
we should test it under Windows, and then under Wine.
...
I have only used the WebPack ISE once, for the programmable logic device
lectures I had at the university last
year, programming a CPLD by following a tutorial, so I have no real
experience there.
I installed the 6.3 ISE with Service Pack 3 under Windows XP.
I downloaded one of the application notes to get some verilog code to
test with.
(http://direct.xilinx.com/bvdocs/appnotes/xapp284.pdf)
I set up a new project for an 3S4000 and added the verilog source, then
simply clicked on synthesize...
Which produced some error about blocking assignments not to be mixed
with non-blocking ones, which
I simply correct by turning some "=" into "<="... ;-)
After that, synthesize, implement design, generate program file worked
with only generating some warnings.
I attached the logfiles for someone to look at who has a bit more
experience here.
So there seems to be some life there, but it should be tested with some
real code someone should cook up for
verifying that all design steps work as we need them.
I for myself will keep reading the verilog lessons and some of the
materials I got from university. The application notes on the Xilinx
website seem to be a good point to get started, too.
(e.g. XAPP473 - Using the ISE Design Tools for Spartan-3 FPGAs -
http://direct.xilinx.com/bvdocs/appnotes/xapp473.pdf )
Benjamin
Started process "Translate".
Command Line: ngdbuild -intstyle ise -dd c:\xilinx\test/_ngo -i -p
xc3s4000-fg900-5 matrix3x3.ngc matrix3x3.ngd
Reading NGO file "c:/xilinx/test/matrix3x3.ngc" ...
Reading component libraries for design expansion...
Checking timing specifications ...
Checking expanded design ...
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 40968 kilobytes
Writing NGD file "matrix3x3.ngd" ...
Writing NGDBUILD log file "matrix3x3.bld"...
NGDBUILD done.
Completed process "Translate".
Started process "Map".
Using target part "3s4000fg900-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 241 out of 55,296 1%
Number of 4 input LUTs: 268 out of 55,296 1%
Logic Distribution:
Number of occupied Slices: 230 out of 27,648 1%
Number of Slices containing only related logic: 230 out of 230 100%
Number of Slices containing unrelated logic: 0 out of 230 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 331 out of 55,296 1%
Number used as logic: 268
Number used as a route-thru: 63
Number of bonded IOBs: 106 out of 633 16%
IOB Flip Flops: 80
Number of MULT18X18s: 1 out of 96 1%
Number of GCLKs: 1 out of 8 12%
Total equivalent gate count for design: 8,644
Additional JTAG gate count for IOBs: 5,088
Peak Memory Usage: 138 MB
NOTES:
Related logic is defined as being logic that shares connectivity -
e.g. two LUTs are "related" if they share common inputs.
When assembling slices, Map gives priority to combine logic that
is related. Doing so results in the best timing performance.
Unrelated logic shares no connectivity. Map will only begin
packing unrelated logic into a slice once 99% of the slices are
occupied through related logic packing.
Note that once logic distribution reaches the 99% level through
related logic packing, this does not mean the device is completely
utilized. Unrelated logic packing will then begin, continuing until
all usable LUTs and FFs are occupied. Depending on your timing
budget, increased levels of unrelated logic packing may adversely
affect the overall timing performance of your design.
Mapping completed.
See MAP report file "matrix3x3_map.mrp" for details.
Completed process "Map".
Mapping Module matrix3x3 . . .
MAP command line:
map -intstyle ise -p xc3s4000-fg900-5 -cm area -pr b -k 4 -c 100 -tx off -o
matrix3x3_map.ncd matrix3x3.ngd matrix3x3.pcf
Mapping Module matrix3x3: DONE
Started process "Place & Route".
Constraints file: matrix3x3.pcf
Loading device database for application Par from file "matrix3x3_map.ncd".
"matrix3x3" is an NCD, version 2.38, device xc3s4000, package fg900, speed -5
Loading device for application Par from file '3s4000.nph' in environment
C:/Xilinx.
Device speed data version: ADVANCED 1.35 2004-11-11.
Resolving physical constraints.
Finished resolving physical constraints.
Device utilization summary:
Number of External IOBs 106 out of 633 16%
Number of LOCed External IOBs 0 out of 106 0%
Number of MULT18X18s 1 out of 96 1%
Number of Slices 230 out of 27648 1%
Number of BUFGMUXs 1 out of 8 12%
Overall effort level (-ol): Standard (set by user)
Placer effort level (-pl): Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): Standard (set by user)
Phase 1.1
Phase 1.1 (Checksum:989eac) REAL time: 4 secs
.
Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 5 secs
Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 5 secs
Phase 5.8
...
Phase 5.8 (Checksum:a913e2) REAL time: 5 secs
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 5 secs
Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 5 secs
Writing design to file matrix3x3.ncd.
Total REAL time to Placer completion: 6 secs
Total CPU time to Placer completion: 5 secs
Phase 1: 1725 unrouted; REAL time: 7 secs
Phase 2: 1486 unrouted; REAL time: 14 secs
Phase 3: 269 unrouted; REAL time: 14 secs
Phase 4: 0 unrouted; REAL time: 15 secs
Total REAL time to Router completion: 15 secs
Total CPU time to Router completion: 14 secs
Generating "par" statistics.
**************************
Generating Clock Report
**************************
+-------------------------+----------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
| CLK_BUFGP | BUFGMUX3| No | 219 | 0.588 | 1.433 |
+-------------------------+----------+------+------+------------+-------------+
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 16 secs
Total CPU time to PAR completion: 15 secs
Peak Memory Usage: 196 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Writing design to file matrix3x3.ncd.
PAR done.
Completed process "Place & Route".
Started process "Generate Post-Place & Route Static Timing".
Analysis completed Fri Jun 23 22:52:59 2006
--------------------------------------------------------------------------------
Generating Report ...
Completed process "Generate Post-Place & Route Static Timing".
Place & Route Module matrix3x3 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 matrix3x3_map.ncd
matrix3x3.ncd matrix3x3.pcf
PAR completed successfully
Started process "Synthesize".
=========================================================================
* HDL Compilation *
=========================================================================
Compiling source file "/../../app/matrix3x3.v"
Module <matrix3x3> compiled
Module <MULT18X18> compiled
No errors in compilation
Analysis of file <matrix3x3.prj> succeeded.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <matrix3x3>.
Module <matrix3x3> is correct for synthesis.
Analyzing module <MULT18X18>.
Generating a Black Box for module <MULT18X18>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <matrix3x3>.
Related source file is /../../app/matrix3x3.v.
WARNING:Xst:1780 - Signal <cntr3_en> is never used or assigned.
WARNING:Xst:1780 - Signal <cntr_cwel> is never used or assigned.
WARNING:Xst:1872 - Variable <i> is used but never assigned.
WARNING:Xst:1780 - Signal <wait1> is never used or assigned.
Found 12-bit register for signal <X>.
Found 12-bit register for signal <Y>.
Found 12-bit register for signal <Z>.
Found 36-bit adder for signal <$n0003> created at line 331.
Found 3-bit comparator greater for signal <$n0008> created at line 351.
Found 2-bit comparator greater for signal <$n0021> created at line 278.
Found 33-bit comparator less for signal <$n0026> created at line 183.
Found 32-bit adder for signal <$n0041> created at line 185.
Found 12-bit register for signal <A_reg>.
Found 12-bit register for signal <A_reg1>.
Found 12-bit register for signal <B_reg>.
Found 12-bit register for signal <B_reg1>.
Found 12-bit register for signal <C_reg>.
Found 12-bit register for signal <C_reg1>.
Found 3-bit down counter for signal <cnt9_wait>.
Found 2-bit up counter for signal <cntr3>.
Found 4-bit up counter for signal <cntr9>.
Found 4-bit up counter for signal <cntr9_out>.
Found 10-bit register for signal <coeff_mux>.
Found 2-bit register for signal <CWEL_reg>.
Found 12-bit register for signal <data_mux>.
Found 2-bit down counter for signal <i_wait>.
Found 32-bit up counter for signal <indexi>.
Found 32-bit register for signal <j>.
Found 10-bit register for signal <KA1>.
Found 10-bit register for signal <KA2>.
Found 10-bit register for signal <KA3>.
Found 10-bit register for signal <KB1>.
Found 10-bit register for signal <KB2>.
Found 10-bit register for signal <KB3>.
Found 10-bit register for signal <KC1>.
Found 10-bit register for signal <KC2>.
Found 10-bit register for signal <KC3>.
Found 36-bit register for signal <P1_reg>.
Found 36-bit register for signal <sum>.
Found 148 1-bit 2-to-1 multiplexers.
Summary:
inferred 6 Counter(s).
inferred 326 D-type flip-flop(s).
inferred 2 Adder/Subtracter(s).
inferred 3 Comparator(s).
inferred 148 Multiplexer(s).
Unit <matrix3x3> synthesized.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 2
32-bit adder : 1
36-bit adder : 1
# Counters : 5
2-bit up counter : 1
2-bit down counter : 1
4-bit up counter : 1
3-bit down counter : 1
32-bit up counter : 1
# Registers : 24
10-bit register : 10
32-bit register : 1
36-bit register : 2
12-bit register : 10
2-bit register : 1
# Comparators : 3
33-bit comparator less : 1
2-bit comparator greater : 1
3-bit comparator greater : 1
# Multiplexers : 14
10-bit 2-to-1 multiplexer : 10
12-bit 2-to-1 multiplexer : 4
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1291 - FF/Latch <P1_reg_35> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_35> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_12> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_13> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_14> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_15> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_16> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_17> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_18> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_19> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_20> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_21> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_22> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_23> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_24> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_25> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_26> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_27> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_28> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_29> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_30> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_31> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_32> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_33> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <sum_34> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_12> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_13> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_14> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_15> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_16> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_17> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_18> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_19> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_20> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_21> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_22> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_23> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_24> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_25> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_26> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_27> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_28> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_29> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_30> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_31> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_32> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_33> is unconnected in block <matrix3x3>.
WARNING:Xst:1291 - FF/Latch <P1_reg_34> is unconnected in block <matrix3x3>.
Optimizing unit <matrix3x3> ...
Loading device for application Xst from file '3s4000.nph' in environment
C:/Xilinx.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block matrix3x3, actual ratio is 0.
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s4000fg900-5
Number of Slices: 259 out of 27648 0%
Number of Slice Flip Flops: 321 out of 55296 0%
Number of 4 input LUTs: 333 out of 55296 0%
Number of bonded IOBs: 105 out of 633 16%
Number of MULT18X18s: 1 out of 96 1%
Number of GCLKs: 1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK | BUFGP | 321 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 5.952ns (Maximum Frequency: 168.011MHz)
Minimum input arrival time before clock: 2.432ns
Maximum output required time after clock: 5.331ns
Maximum combinational path delay: No path found
=========================================================================
Completed process "Synthesize".
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