Timothy Miller wrote:
On 7/20/06, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
I missed something here. Is the memory 64 bits wide -- 4 @ 16 bit wide
chips? A two read burst gets you 4 pixels. But, you have a 8 pixel
wide FIFO.
There are 8 chips, 16 bits wide, for a 128-bit bus. But that bus is
running at 400MHz. Plus, we always have to do bursts of length 2, so
internally, we just carry around 256-bit data at 200MHz (in the memory
controller--other things produce/consume it more slowly via fifos).
{This should probably be in the spec since it is something in the specs
of most graphics boards.}
The spec seems to say:
128 Megabytes (four 256 megabit chips)
This is correct math wise, however from what you said, it appears that
it isn't correct. I guess that this should be:
128 Megabytes (eight 128 megabit chips)
--
JRT
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