On Tue, Aug 01, 2006 at 08:19:42AM -0400, Timothy Miller wrote:
> On 8/1/06, Koen De Vleeschauwer <[EMAIL PROTECTED]> wrote:
> >I've been wondering which DVI dotclocks will be available on OGD1.
> >There seem to be three oscillators; 13.5 MHz, 14.318 MHz and 44.647 MHz.
> >13.5 Mhz is a well-known sample rate for digital TV,
> >14.318 MHz a well-known sample rate for NTSC (and used in PCs).
> >Where does the 44.647 MHz come from?
> 
> I don't recall exactly what Howard put on there, but the Xilinx DCMs
> are capable of producing clocks with a variety of different multiplier
> and divider values.

Yes, you can program the DCM (digital clock managers) to multiply an incoming 
frequency by a fraction n/d, where n=2..32, and d= 1..32.

On Virtex-4 you can reconfigure these factors on the fly while the FPGA is 
running. (check "Use reconfiguration pins" in the wizard).
I could be wrong, but AFAIK the multiply/divide factors of the Spartan-3 DCM 
can only be specified statically, in the verilog source, as // synthesis 
attribute. 
There has been a small thread about this on comp.arch.fpga "Programmable 
frequency synthesizer with Xilinx DCM". 
http://www.fpga-faq.com/archives/87700.html
> Subject: Re: Programmable frequency synthesizer with Xilinx DCM
> From: "Peter Alfke" <[EMAIL PROTECTED]>
> Date: 2 Aug 2005 15:09:39 -0700
> 
> Present generation: Spartan3 plus external PLL for higher freq. and
> less jitter.( <100 ps)
> Next generation: Virtex-4 FX (needs MGTs)
> Peter

Correct me if I'm wrong, but I only see three possibilities:
- using an external PLL. I see no external PLL in the schematic, however.
- using a PLL in another chip on the board, eg. the Conexant. CLKO of the 
Conexant seems unconnected, however.
- or reloading  the FPGA with a different bitstream whenever the modeline 
dotclock changes.

Which do you use?

regards,

koen

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