On 8/25/06, Timothy Miller <[EMAIL PROTECTED]> wrote:
On 8/25/06, Jon Smirl <[EMAIL PROTECTED]> wrote:
> That is going to be hard to program. GART memory is easy to use, just
> ask the kernel for a chunk of it. It will appear to the app as
> contiguous memory since the kernel GART driver will set up the page
> tables in the app.
Will it appear contiguous to the GPU also? If so, then good.
In an ATI card:
You have the internal address space
Into this address space you map the PCI region of the GART hardware.
There is a BAR equivalent in the video card.
The GPU doesn't know if it is accessing VRAM or mapped space.
When it accesses the mapped space it turns into a PCI cycle.
The PCI cycle is picked up by the motherboard GART device.
The GART device turns the PCI address into a physical RAM address with the maps
These mapping tables scramble the pages into paged CPU space.
The GPU read/write now ends up in the right place in system memory.
User space apps can get to this two ways, both work
1) They map the GART region from PCI space
2) Their page table includes entries that mimic the GART mapping
If a user space app reads/writes from GART space nothing happens on
the GPU. GART read/writes from an app only impact system memory. This
system memory is marked non-pagable, non-cachable. The GART region in
PCI space is marked write combine.
Other points in the memory model:
Part of the VRAM is always mapped by the CPU. This is how software
fallbacks are implemented.
When in command stream mode the PIO registers are rarely used by the
CPU. This is because the internal GPU command stream can also write to
the same registers.
GPU operations are controlled by writing to these registers. For
example bilblt. I'm simplifying but there is really only one command
type in a command stream. The command just consists of a bunch of
register addresses and the values to write to them. There is no bitblt
command, just this generic command that can write to the registers
that control the bilblt engine. You can totally control the chip this
way, even change the video mode.
You can do every command externally by turning off the command stream
and writing the registers via PIO. That is a good way to test the
chip. This model is why Radeons have 2,000 registers.
--
Jon Smirl
[EMAIL PROTECTED]
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