Timothy Miller wrote:
On 9/6/06, Dieter <[EMAIL PROTECTED]> wrote:
> Traversal is going to be subject to many of these concerns.
Timothy, any thoughts on using a DSP?
In place of OGA or as an add-on?
The Ti is fixed point so it wouldn't be able to do OpenGL. The Sigma
chips are hardware decoder chips for MPEG and other codecs so that is
all they would do.
There have been many discussions about using DSPs. They can do almost
none of the major features of OGA, and those that it can do (like the
rendering), it would be unacceptably slow, no matter how fast it's
clocked.
That isn't what we are talking about here. And, most DSPs that I have
been looking at are fixed point. TI offers a 1 GHz one which wouldn't
be slow. But 600 MHz appears to be fast enough for MPEG decoding.
As an add-on, I'd rather not deal with the integration problems this
time. Perhaps for OGA2, we can do things like that (put a DSP bus on
the ASIC), but for now, that's biting off more than we can chew and
making things unnecessarily expensive for the common case.
There are clearly integration issues. The TI chips probably wouldn't be
able to access memory at 200 MHz DDR so that would be an issue that I
would solve with a very small read cache and a posted write buffer.
But, IIUC the same issue exists for other parts of the design so it the
same hardware could be used for both, it wouldn't be much of an issue.
The way the TI would work is that it would read the encoded frame into
its private SDRAM from system memory with its DMA, convert it and resize
it and then output it to the window in the video buffer with DMA.
The chip has 64 DMA channels and multiple address spaces.
Note that if it is fast enough that you might be able to use the DMA in
the TI chip for the video refresh controller. It might also do other
DMA jobs.
It would be more useful if they had a model that supported DDR/DDR2
SDRAM. I realize that 133 MHz SDR DRAM is a bit slow for the RAM access
and it appears that it would only support 50 MHz system bus access which
would be an issue since it would have to use the DRAM interface for fast
system bus access and that means intermediate logic if we use a stock chip.
The Sigma chip would be strictly a codec coprocessor which is what it is
designed to do. It would read the encoded frame and output the decode one.
--
JRT
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