On Thu, 2006-10-05 at 11:15 -0400, Timothy Miller wrote: > On 10/2/06, Nicholas <[EMAIL PROTECTED]> wrote: > > > Yes, the interface is DDR. It has a total of 9 modes (set with IN_MODE > > pins). I am going to describe them in terms of pins_up[11:0] and > > pins_down[11:0], which are on rising and falling edge of clockin, > > respectively. > > 0000: 24 bit RGB. > > pins_up[9:11]=g[2:4] > > pins_up[4:8]=b[3:7] > > pins_up[3]=g[0] > > pins_up[0:2]=b[0:2] > > > > pins_down[7:11]=r[3:7] > > pins_down[4:6]=g[5:7] > > pins_down[1:3]=r[0:2] > > pins_down[0]=g[1] > > This is what I need. Thank you. > > Why did you reverse the bit order? I just want to be sure that I know > where the highest order bits go. With then reversed, I can't be sure > if you mean that, for instance, g[7] is high-order or low-order. I probably shouldn't have switched the order, but it is too late now. That is the direction they are on page 1-6, so I just copied how it was layed out (and I was thinking in Verilog at that point; here is the result :-)). Here is what I meant by the numbers: > pins_down[4:6]=g[5:7] this means that pins[4] on the falling edge of clock is g[5], pins[5] on the falling edge is g[6], and pins[6] on the falling edge is g[7].
same thing here: > pins_up[0:2]=b[0:2] pins[0] on the rising edge is b[0], etc. does that clear things up? nick _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
