On 10/2/06, Simon Persson <[EMAIL PROTECTED]> wrote:
Assuming the encoder to be used is the CX25874...
Yes.
The interface is DDR, 12 bit wide. Data can be divided up in two different ways for each of 24 bit RGB, 24 bit YCbCr or 16 bit YCbCr. Also has one mode for 16 bit RGB with 8 bit latched in on each edge. Now...was that useful??
Yeah, we're getting there. There are 12 data pins on the chip, so I'm assuming that half of the bits are accepted on the rising edge, and half are accepted on the falling edge. Is that correct? And how exactly are the 24 bits split into the two 12's? _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
