On 12/20/06, Peter TB Brett <[EMAIL PROTECTED]> wrote:
On Wednesday 20 December 2006 09:32, Roger Luethi wrote:


Speaking of which, how close are we to OGD1 release?  Days, weeks, months or
years?


I'm not sure, but I think Howard may have gotten some video on the
screen.  For testing, we've cobbled together code that belongs to us
(that has already all been released), along with code that doesn't
(that we can't release).  One of the concerns was, if we had a large,
complex design in there, would we end up running out of some resource
(like routing resources or whatever) that could be alleviated by
moving external pins around.  This is something we've encountered
before a few times.

We could have started selling OGD1 boards back in November, but we'd
be taking the risk of selling boards that would come back because they
were faulty, and we just could not handle the cost of that kind of
mistake.  Every little decision we make comes with a complement of
risks.  When we're trying to do something expensive based on our own
personal money, that we have to get exactly right the first time, we
may find ourselves being overly conservative.

We know for certain that the PCI bus is wired correctly.  We're able
to perform isolated transactions (with someone else's PCI controller
that has been used in other designs), although we haven't beaten it to
death yet.  The trace lengths are in spec, so we don't really expect a
problem there.  The bridge between the XP10 and the 3S4000 is
logically wired right, but the sampling phase window on the signals at
200MHz (100MHz DDR) is tighter than we had expected, and we're trying
to make sure we don't need a relayout to tighten up the variation in
lengths of the different traces.  Memory and video have had signals on
them, but not nearly enough testing has been done to certify them, so
to speak.
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