The PCI logic (simulation model) is starting to shape up.  I've tried
a variety of different tests, and the signals appear to be wiggling in
accordance with the PCI spec.  There's still plenty to do.  I need to
comb through the spec carefully and ensure that my design is
conforming properly in each case.  Additional tests include making the
master and target each intentionally misbehave and ensure that the
other doesn't get stuck in an invalid state.  Another test will be to
interface my designs with the OpenCores PCI controller and see how
well they talk to each other.

--
Timothy Miller
http://www.cse.ohio-state.edu/~millerti
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