On 1/2/07, Patrick McNamara <[EMAIL PROTECTED]> wrote:
Deep pipelines are your friend. :) Actually, they 3S4000 really should do little more than pass the data through. Obviously, it needs to handle the RAM refresh, but beyond that, in capture mode, I would argue that all it really needs to do is track the memory location for the next sample and act as a pass through for the bus samples. There is no need to read from the memory during capture and there is likely no need to write to it during upload. Any processing or program store for an embedded core should use the DRAM/BRAM available in the 3S4000. Since I don't think we will be gate limited in either FPGA, brute force is a perfectly viable option. Function over form as it were.
The number of pins between the XP10 and the 3S4000 is about 40. At 200MHz transfer rate, we thought we'd have a large data eye for the I/O receivers, but we don't. That doesn't bode well for higher clock rates. Now, the thing is, at 400MHz, very little changes from clock to clock, because the PCI bus just doesn't transition that fast. We're guaranteed to get LOTS of repetition in the signal, which means a RLE compression between the chips is very doable. -- Timothy Miller http://www.cse.ohio-state.edu/~millerti _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
