On 4/22/07, Petter Urkedal <[EMAIL PROTECTED]> wrote:
Another thing, I realised that the only instructions which require a
bit-bucket are branches.
For writes. Do none require the bitbucket to read zero? Or are you
always using immediate for that?
After changing the format, we have one free
bit in the branching instruction words. We could use that to
enable/disable the write-back, it's a simple test which can be done in a
non-critical place. The question is this only saves us one out of 32
registers, so is there any better use of this bit?
MIPS is not sacrosanct. If we decide that we don't need r0 to the the
zero bitbucket, maybe we should. It takes a lot less logic to compare
none flag bit than to check if a 5-bit number is zero. (In an FPGA,
not much less, but it still introduces propagation delay.)
Where do I find the definitions of these fifos?
There are no such definitions. I made them up randomly on the spot.
When we design the surrounding logic, we'll give them numbers.
But, what's the relation to the shunts. The above operates on 32 and 64
bit words. The current shunts have 8 bit granularity, and was more
intended for shuffling around colour components of pixels, and as a
substitute for the lack of 8 bit and 16 bit instructions. The same
thing take be done with one or two {shift, and, or}, so it's probably
not that useful. I'll take it out. Then, there will be 5 bits free in
the move instruction, so we'll reserve those for enumerating additional
unary instructions we might need.
Shuffle might be nice. If we can come up with some important uses for
it, we can keep it. But frankly. I'm not sure when we'll ever use 8
or 16 bit words for anything. OGA is a 32-bit only design.
One thing we'll do when processing command packets is some sort of
bit-picking thing where we do something or not depending on the value
of a bit in a register value. For instance, the packet header can
contain a set of flags for option registers. We'll walk down the list
in order and whenever a flag bit is set, we'll pop another word out of
the DMA fifo and write it to the correct register in the GPU.
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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