On 2007-04-22, Paul Brook wrote:
> > == Simple Instructions ==
> >
> > The simple instructions combine a register and either a register and an
> > immediate, and store the result in a register. The original simple
> > instructions are as follows. The last parameter is the write-back
> > register.
>
> I realise it's not a critical issue, but most RISC assembly syntax put the
> destination register first. Every time I have to deal with a "backwards"
> syntax it takes me a while to re-adjust.
I'm not familiar with RISC programming. Is SPARC assembly one of those
counter cases to the rule?
http://docs.sun.com/app/docs/doc/816-1681
http://www.cs.clemson.edu/~mark/sparc_assembly.html
I find the (src, src, dst)-ordered assembly easier myself, since reading
it from left to right means following the data flow. But, it's not too
difficult to change the assembler if I am in minority on this.
> > == Branching Instructions ==
> >
> > The branching is controlled by 3 bits
> >
> > * negation of branch condition
> > * branch if zero
> > * branch if negative
>
> I notice that you haven't provided any way to access the ALU carry flag. This
> is going to make unsigned comparisons and doubleword (64-bit) arithmetic very
> hard. It's not impossible (I've worked on compiler ports for such machines),
> but gets really ugly. FWIW MIPS exposes it via the sltu instruction.
>
> If you've deliberately decided this isn't an important feature for this
> application then it's maybe worth mentioning that in the architecture docs.
Good point, though I've seen Tim's take on this, and I can't imagine at
the moment what we'll use 64 bit datatypes for. But, there is room for
it in the instruction word if we need it, so we can document it for the
moment, and hope we'll discover the need before this goes onto an ASIC.
If we were to add it; in the current CPU we could use the carry bit
which I assume the FPGA already will put on our adder, to add an
instruction similar to mulh for adds. E.g. to add (r1, r0) and (r3, r2)
into (r5, r4):
add r0, r2, r4
addh r0, r2, r5
add r1, r5, r5
add r3, r5, r5
I can't see a way to do 64 bit adds in less that 4 instructions without
introducing some sort of status register which needs to be saved in case
of async control flow.
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