On 2007-04-21, Dieter wrote:
> > > > > >Are we missing any important operators here? (Remember that the
> > > > > >assembler will provide some derived operators like "neg", "not",
> > > > > >"sub",
> > > > > >etc, and that branching instructions are separate and memory
> > > > > >instructions are orthogonal to these operators.)
>
> ( suggestion of NOP )
>
> > Yes, I'll make sure to add it to the assembler, along with other derived
> > operators like "neg", "not", "sub", "jump" etc.
>
> It might be useful to post the full set of instructions that the
> assembler will provide, regardless of whether they are native
> or derived.
Good idea, after all I'm appealing to potential programmers. Now, you
can fill me in on assembler instructions too.
== Simple Instructions ==
The simple instructions combine a register and either a register and an
immediate, and store the result in a register. The original simple
instructions are as follows. The last parameter is the write-back
register.
move REG, REG
and REG, (REG|IMM), REG
or REG, (REG|IMM), REG
xor REG, (REG|IMM), REG
shift REG, (REG|IMM), REG
shiftu REG, (REG|IMM), REG
add REG, (REG|IMM), REG
rsub REG, (REG|IMM), REG
mull REG, (REG|IMM), REG
mulf REG, (REG|IMM), REG
mulh REG, (REG|IMM), REG
mulhu REG, (REG|IMM), REG
These give rise to the following derived instructions:
noop noop ==> and r0, r0, r0
not REG, REG not x, z ==> xor x, -1, z
neg REG, REG neg x, z ==> rsub x, 0, z
and IMM, REG, REG
or IMM, REG, REG
xor IMM, REG, REG
add IMM, REG, REG
sub (REG|IMM), REG, REG sub x, y, z ==> rsub y, x, z
sub REG, IMM, REG sub x, y, z ==> add x, -y, z
mull IMM, REG, REG
mulf IMM, REG, REG
mulh IMM, REG, REG
mulhu IMM, REG, REG
We could also add shortcut for cases when one of the operands is the
same as the write-back register. I suggest we limit this to the
symmetric cases, excluding mulh and mulhu:
not REG
neg REG
and (IMM|REG), REG
or (IMM|REG), REG
xor (IMM|REG), REG
add (IMM|REG), REG
mull (IMM|REG), REG
mulf (IMM|REG), REG
== Memory Instructions ==
For each simple instruction iiii, there is a load instruction:
iiii REG, (REG|IMM) load REG given iiii REG, (REG|IMM), REG
iiii IMM, REG load REG given iiii IMM, REG, REG
iiii REG load REG given iiii REG, REG
For each immediate simple instruction iiii, there is a store
instruction:
iiii REG, IMM store REG given iiii REG, IMM, REG
iiii IMM, REG store REG given iiii IMM, REG, IMM
iiii REG store REG given iiii REG, REG
We could make derived instructions for the most useful cases:
load REG + (REG|IMM), REG load x+y,z => add x, y load z
load IMM + REG, REG load x+y,z => add x, y load z
load REG, REG load x, z => add x, 0 load z
store REG, REG + IMM store z,x+c => add x, c store z
store REG, REG store z, x => add x, 0 store z
== Branching Instructions ==
The branching is controlled by 3 bits
* negation of branch condition
* branch if zero
* branch if negative
E.g. if both branch-if-zero and branch-if-negative bits are set, then
the condition is "branch if non-positive". In the following
instructions, the first operand is the test-register, the second is the
branch address. For the three-parameter instructions, the return
address is written to the last parameter.
jfalse REG, (REG|IMM)
jneg REG, (REG|IMM)
jzero REG, (REG|IMM)
jnpos REG, (REG|IMM)
jtrue REG, (REG|IMM)
jnneg REG, (REG|IMM)
jnzero REG, (REG|IMM)
jpos REG, (REG|IMM)
jfalse REG, (REG|IMM), REG
jneg REG, (REG|IMM), REG
jzero REG, (REG|IMM), REG
jnpos REG, (REG|IMM), REG
jtrue REG, (REG|IMM), REG
jnneg REG, (REG|IMM), REG
jnzero REG, (REG|IMM), REG
jpos REG, (REG|IMM), REG
from which we derive
jump REG jump y ==> jtrue r0, y
jump REG, REG jump y, z ==> jtrue r0, y, z
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