On 7/27/07, Attila Kinali <[EMAIL PROTECTED]> wrote:
> Moin,
>
> On Thu, 26 Jul 2007 14:07:47 -0700
> "Timothy Normand Miller" <[EMAIL PROTECTED]> wrote:
>
> > Thanks to some helpful people on the list, we were able to figure out
> > why in our test environment, framebuffer writes were slow.  We changed
> > the way the mapping worked to enable write combining, and it now gets
> > very good throughput.
>
> Could you explain what you did? For reference and to stanch my
> curiosity :)

I copied some code straight out of X.org.  I don't have the source
tree available (it's in the machine that's on its way back via FedEx
ground).  Deep under Xserver/hw, in some xfree86 directory, you can
find a function called "xf86MapVidMem."  I copied what I needed from
that.  Basically, there's an ioctl you can make to a fd opened on
/dev/mem that will change the MTRR settings.

>
> > But we've since noticed that READS only get
> > about 4 megabytes/sec.  Does anyone have any insight into this?
> > Surely, there must be some way to enable an optimization to reads as
> > well, no?
>
> Have you set the "prefetchable" bit in the base address registers?
> To my understanding, if that is set, read operations should always
> get one cacheline.

Prefetchable is definitely set.

> Alternatively use memcpy_fromio(), though i doubt that this does
> more than 4 byte reads.

I'll have to look into that.  Ultimately, we want to do DMA, but I
thought it would be nice to have an unaccelerated DDX not suck quite
so bad.  :)


-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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