On Sat, 20 Oct 2007 12:19:47 -0400
"Timothy Normand Miller" <[EMAIL PROTECTED]> wrote:
> If you want to help out and look for bugs, I would suggest starting
> with the TV-out on page 15 of the schematic. (Note that the page
> numbers are not in ascending order.) This is the least-tested part of
> the design and is therefore the likeliest to have a problem.
Some preliminary feedback from a first quick look:
Sheet 1:
Is there a special reason to use U14 instead of connecting
REQ64 and REQ64_BE directly to the XP10?
Sheet 3&6:
I think an additional 10uF X5R for each power rail of each
FPGA is justified, maybe even more.
Sheet 7&8:
Isn't V_ref supposed to be generated at a central point?
The way it is generated here does certainly work, but we'll
get just with 9 different values for V_ref. And the resistors
have to be 1% types instead of 5% types.
I would also additionally place a 1uF X5R/X7R near each DRAM module.
I once had a problem with ground bounces at DRAM chips and it
was a hell to debug...
Sheet 13:
I guess pin 93 and 94 are the two stress releave pads.
If so, i would connect them to ground too, as the connector
seems to have some kind of shielding anyways, even without
additional ground plate
Sheet 15:
Shouldn't the clamping diodes D5 and D6 be on the other side
of the inductor, ie directly at the connector?
Sheet 16-18:
The datahseet of the MAX8578 recomends an 47uF capacitor with
an ESR of 5mR for output (optionaly a second one of it), but the 22uF
specified capacitors have each an ESR of 1mR, resulting in a total
ESR of 0.25R (factor 10 below recomended). Are you sure that the
control loop of the MAX8578 is still stable with such a low ESR?
Also you put in three times the same inductor. Do all calculations
lead to the same inductance or has this been done for cost reasons?
Attila Kinali
--
Linux ist... wenn man einfache Dinge auch mit einer kryptischen
post-fix Sprache loesen kann
-- Daniel Hottinger
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