Moin,
On Sun, 21 Oct 2007 20:59:27 -0400
"howard parkin" <[EMAIL PROTECTED]> wrote:
> On 10/21/07, Attila Kinali <[EMAIL PROTECTED]> wrote:
> > Sheet 3&6:
> >
> > I think an additional 10uF X5R for each power rail of each
> > FPGA is justified, maybe even more.
>
> I think so too, but its near impossible to get the caps
> close enough to the FPGA to do any good. What we have
> here is what the layout of the V1 card would permit.
Actually these capacitors do not need to be really at
the FPGAs, althoug the nearer the better. What they
have to provide is to buffer energy surges that the
smaller caps cannot. So it would be enough to have
some larger caps around the FPGAs, given that you have
some low inductance power lines.
What i ususaly do is to place the small caps according
to the app notes below the FPGA (or any other high
frequency digital circuit) and 1 to 8 10-47uF caps
in the vincinity (mostly within 0-2cm distance)
and connect everything by large, low inductance
power planes.
> > Sheet 15:
> >
> > Shouldn't the clamping diodes D5 and D6 be on the other side
> > of the inductor, ie directly at the connector?
>
> Yes, its strange. But I checked the Conexant schematic,
> and we've copied it correctly. I guess it's more important
> to protect the IC rather that the passives.
Actually, they would protect the IC better if they would
be on the other side of the filter, as they have some
switch on delay within which the IC can be damaged.
But yes, i saw that in the datasheet too, so i guess
it's ok.
Attila Kinali
--
Praised are the Fountains of Shelieth, the silver harp of the waters,
But blest in my name forever this stream that stanched my thirst!
-- Deed of Morred
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