On 07/11/2007, Patrick McNamara <[EMAIL PROTECTED]> wrote: snip> On a technicality, I might do this as follows: > > module GATE2INAND(a,b,x); > input a, b; > output x; > assign x=a&b; > endmodule > > module IC7408(a0, b0, a1, b1, a2, b2, a3, b3, x1, x2, x3); > input a0, b0, a1, b1, a2, b2, a3, b3; > output x1, x2, x3; > > GATE2INAND AND0( .a(a0), .b(b0), .x(x0)); > GATE2INAND AND1( .a(a1), .b(b1), .x(x1)); > GATE2INAND AND2( .a(a2), .b(b2), .x(x2)); > GATE2INAND AND3( .a(a3), .b(b3), .x(x3)); > endmodule > > My reason for doing this is that if we put together a library of gates > and chips like this, the you could take a gschem netlist and generate > Verilog RTL for the circuit (assuming it's all digital of course). Also > for someone just learning Verilog and potentially digital logic, > building simple blocks first, then layering it all together may make > more sense. In the end the result (and I would hope synthesis) would be > the same. Obviously, not all the 74xx chips make sense to be broken > down this way, but many do. In fact you can even find the logic > diagrams for many on their data sheets. > > Patrick M
This potential library - How can we do this? It seems a good opportunity for the list and lurkers to learn by doing some of the basic chips, we get a library and hardware becomes more open all at the same time. Were/who would store the library? OGP, OHF? another? What license would be most useful ? jb that sound you hear is another tear appearing through the walls of vendor lockin. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
