Reimar Döffinger wrote:
On Sun, Nov 11, 2007 at 03:48:40PM -0500, Timothy Normand Miller wrote:
On 11/11/07, Attila Kinali <[EMAIL PROTECTED]> wrote:
I personaly do not like the "negation bar" in source code
as i either use positive logic (there is no need for negative
logic within a synchronus design) or have few explicit signals
for which it is clear by their name that they are negative logic
(which are at the interfaces to the outside world only anways).
Let me expose for a moment my ignorance of some of the analog aspects
of digital circuit design. What is the primary reason for so many
negative logic signals? My best guess is that one of the logic levels
draws more current, but I'm probably going down the wrong track.
Isn't it mostly reset that is negated? There the problem is that on
power on when your power slowly comes online, how would you be able to
drive it high? It's much simpler to keep it to low, all you need if
you're lazy is a capacitor and a resistor.
I'm not so sure about e.g. interrupts, but I'd assume that it might be
because interrupt lines usually have a pullup/pulldown resistor, so your
drivers must work against additional load, and driving a line low
against a load seems to be easier.
I always assumed what was said above about reset & RC. The following
also sounds plausible:
"Most control signals in electronics are active-low signals (usually
reset lines, chip select lines and so on). This stems from the fact that
most logic families can sink more current than they can source, so
fanout and noise immunity increase. (The reason for this is ultimately
related to the fact that electrons are negatively charged.) It also
allows for wired-OR logic if the logic gates are
open-collector/open-drain with a pull-up resistor."
http://en.wikipedia.org/wiki/Active_low
Of course, all of this is moot for targeting FPGAs, where active-low
logic is pointless (though usually harmless, I suppose). For what it's
worth, I think most FPGA companies' synthesis guidelines recommend
synchronous active-high resets (certainly Xilinx, anyhow).
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