On 12/11/2007, Mark <[EMAIL PROTECTED]> wrote: > Josephblack wrote: > > We should standardize how to write inputs/outputs that are active lows > > in the library we have started.
> I think most of the code on OpenCores (both Verilog and VHDL from my > recollection) uses a "_n" suffix (e.g., "rst_n"). > > The cores that come with Xilinx's EDK (VHDL) use the following: > ------------------------------------------------------------------------------- > -- Naming Conventions: > -- active low signals: "*_n" > -- clock signals: "clk", "clk_div#", "clk_#x" > -- reset signals: "Rst", "rst_n" > -- generics: "C_*" > -- user defined types: "*_TYPE" > -- state machine next state: "*_ns" > -- state machine current state: "*_cs" > -- combinatorial signals: "*_com" > -- pipelined or register delay signals: "*_d#" > -- counter signals: "*cnt*" > -- clock enable signals: "*_ce" > -- internal version of output port "*_i" > -- device pins: "*_pin" > -- ports: - Names begin with Uppercase > -- processes: "*_PROCESS" > -- component instantiations: "<ENTITY_>I_<#|FUNC> > ------------------------------------------------------------------------------- For active low, a _n suffix it is - Thanks everyone who helped. I have updated the wiki page. Those who have added an entry, can we check them, and possibly update them - we have a couple of minor updates: All Inputs and outputs are individual pin outputs All Active Low names end with _n More explicit logic - no one line magic incantations<g>. thanks jb ps Should we add the above list on the HDL page - how much would suit our work? _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
