2007/11/12, Attila Kinali <[EMAIL PROTECTED]>: > > On Sun, 11 Nov 2007 15:48:40 -0500 > "Timothy Normand Miller" <[EMAIL PROTECTED]> wrote: > > > On 11/11/07, Attila Kinali <[EMAIL PROTECTED]> wrote: > > > > > I personaly do not like the "negation bar" in source code > > > as i either use positive logic (there is no need for negative > > > logic within a synchronus design) or have few explicit signals > > > for which it is clear by their name that they are negative logic > > > (which are at the interfaces to the outside world only anways). > > > > Let me expose for a moment my ignorance of some of the analog aspects > > of digital circuit design. What is the primary reason for so many > > negative logic signals? My best guess is that one of the logic levels > > draws more current, but I'm probably going down the wrong track. > > Well, it is to some part historical and to some part by convention. > Most of it comes because we (arbitrarely) choose GND as the refernece > level and build electronics in a way that they measure voltage levels > against GND. Thus, as Reimar already mentioned, it is easier to pull > a reset low during power up and prevent the circuit from behaving > incorrectly. > Ofcourse the same can be done with a positive logic reset and pulling > up, if the input circuit would be build to reference against Vcc instead > of GND. But as i said, we do (normaly) measure voltages against GND. > This is the part that comes by convention. > > The other reason why bus signals are often negative logic is, > that they needed a wired-or using open collector resp open drain > circuits to drive them low. Historicaly NPN and N-channel transistors > had a higher current drive because they use electrons as current > carriers which have a higher mobility than holes. These days PNP > and P-channel transistors can be build with same speed/current drive > as their counter parts, so this reason does not hold anymore > (at least in "normal" electronics). But it became a convention > and thus is still used everywhere. > > That said, none of these reasons hold within a digital CMOS circuit > because N and P channel FETs have to be balanced and thus using > positive logic is absolutely equivalent to negative logic > (given that the reset circuit works properly). And thus i prefere > the positive logic within designs because usualy they are easier > to understand. > > Attila Kinali
There are also some other factor like the first IC where NMOS, where only the negative part had a drive. Since control signal have a great fanout it was necessary to have the sharpest transition possible. The positive part of the signal was given by a pull-up resistor. Given the architecture each time you were driving the signal to a zero you where dissipating power for driving the line and driving the pull-up to zero. Also all gates in CMOS technology are inverted gates if you want to work in not inverted logic you must add an inverter as an output. Most synthesis tool will do it for you but not in a optimal fashion. A lot of cell in a standard cell are also optimised for receiving negative control signal like a flip-flop with a reset, You would see a difference of size between the asyncronus or syncrone reset and if the reset is positive or negative . Because of the complexity and the size requirement for cmos gate most of the logic in a standard cmos library are not balanced except if required by the person making the synthesis. Because for a balanced gate you need a Pmos being ~3 times the size of it Nmos counter part. The difference of width of a cell in a cell between a balanced and an unbalanced one could vary from a factor of 1(inverter) to a factor of 10 or more for some of the more complex gates.
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