Terry Hancock wrote:
John Griessen wrote:
I've made a first cut at diagramming OGD1
It looks implausibly simple, but as such it's terrific!
Will it have to get much more complex, or is this really what the design
comes down to?
It needs some more... a branch for every type of chip,
showing all flows of data on wires, but not all wires.
It stays on one page though. Extra detail, if needed for this diagram
can go on page 2. gschem is my favorite choice of tools for
schematic and netlist creation -- able to make a combined schematic with
embedded verilog,
but not yet able to make a verilog netlist from the top. It's still useful to
make a schematic
representation for your top level verilog model, just as a way to think about
it.
It's not too far off that gschem will be able to do such a verilog design
method,
generating top level verilog "wires" to connect verilog modules with the help
of icarus verilog. The idea of that is not so much to simulate the whole
board, but to automate some
of the checking of connections. You would make a subset schematic and the two
FPGAs to simulate
them both clocking at once. That would need to glue logic in verilog too.
If you are interested, why not install geda packages on your computer and try
opening it and
moving things around? Gschem is free-open, so it's a good match for open
hardware collaboration.
On a debian machine, this would be like:
apt-get install geda
gschem OGD1-schem-top.sch
since all the symbols are embedded in that drawing. Otherwise, there is a
little library setup to do.
John G
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