I'm doing the top-level modules, gluing stuff together, and this is,
by far, the most error-prone part of the whole job, at least for me.
It's a tedious process creating module instances and especially the
wires that interconnect them. As such, I really need a LOT of people
to look over this. These things are absolutely critical to get right.
I also have a cold with really bad sinus pressure, making this even
worse.
Here's a partial list of things to look for:
(1) You'll have two module instances that are connected by some wire.
For instance:
modulea a (.somewire(xx));
moduleb b (.somewire(xx));
If you forget to declare the wire xx, Verilog will infer it as a
single bit. That's bad. If you declare the name wrong, same effect.
We need to make sure that both instances are preceded by a proper wire
declaration:
wire [63:0] xx; /// or whatever the correct width
(2) Addresses -- Different parts of the design use addresses with
different numbers of bits because they refer to different word sizes.
Here's how I think the 1GB memory address space should work out:
PCI addresses are 32-bit, but we want only [29:0]
Stripped of the byte offset, that gives us [29:2] or [27:0]
(Address of 32-bit word)
For 64-bit words (wanted by the arbiter), that's [26:0]
Since there are four memory controllers, we chop off again
the lower 2 bits, leaving us with [24:0] into an arbiter.
However, the memory space isn't that big, leaving [22:0] to the
memories. (Ignore top two.)
I need other people to look at all of the address busses and make sure
that they're sized right and that all the right shifts are happening.
(3) Sane naming of wires and ports. I have violated this all over the
place, and I need others to help me fix it. I'm impatient and have
huge numbers of things to hook up. Others can help focus on small
pieces and clean them up.
If two modules connect directly, we should have wire names that
explain the connection. For instance a direct connect from the the
address decoder to the bridge in the XP10 has a dec2br_ prefix. Other
places should imitate this. Another complication is where there's a
fifo in between. I haven't decided on how best to handle this.
I'm about to check some stuff into SVN. I need someone to take over
each top-level module, please. There's enough there that the learning
curve should be low.
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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