Timothy Normand Miller: >(1) You'll have two module instances that are connected by some wire. >For instance: > >modulea a (.somewire(xx)); >moduleb b (.somewire(xx)); > >If you forget to declare the wire xx, Verilog will infer it as a >single bit. That's bad. If you declare the name wrong, same effect. >We need to make sure that both instances are preceded by a proper wire >declaration: > >wire [63:0] xx; /// or whatever the correct width
Wrote a quick and dirty perl script[1], that can validate some of the wires/buses. However, it's quite unfinished ( Haven't gotten all the verilog syntax in yet ), but for now it can at least get some of the worst errors ( I believe ). See if it looks like a good idea (tm) and let me know if it's worth continuing. Good night, Kenneth [1] http://langly.org/og/check.pl -- Life on the earth might be expensive, but it includes an annual free trip around the earth. Kenneth Østby http://langly.org _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
