On 12/14/07, Kenneth Ostby <[EMAIL PROTECTED]> wrote: > Timothy Normand Miller: > >(1) You'll have two module instances that are connected by some wire. > >For instance: > > > >modulea a (.somewire(xx)); > >moduleb b (.somewire(xx)); > > > >If you forget to declare the wire xx, Verilog will infer it as a > >single bit. That's bad. If you declare the name wrong, same effect. > >We need to make sure that both instances are preceded by a proper wire > >declaration: > > > >wire [63:0] xx; /// or whatever the correct width > > Wrote a quick and dirty perl script[1], that can validate some of the > wires/buses. However, it's quite unfinished ( Haven't gotten all the > verilog syntax in yet ), but for now it can at least get some of the > worst errors ( I believe ). See if it looks like a good idea (tm) and > let me know if it's worth continuing. > > Good night, > > Kenneth > > [1] http://langly.org/og/check.pl
Awesome. If we can develop some tools like this, it'll really make our life easier. In the long run, it would be nice to have tools that _generate_ this code. This is one of the reasons I started on HIDE. (If we finish the VGA stuff before the end of the break, maybe I'll get back onto that.) -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
