Lourens Veen wrote: > I've updated the status of a number of VGA Code Sprint tasks on the > wiki. For some of them I don't know their current status though, so if > anyone can enlighten me as to the following... > > Task 1.4: Design logic for the primary FPGA to process "engine" register > accesses. For configuration of the memory controllers and video > controller and so on. Is this built into the bridge? Or is it still to > be done? > >
I believe this is done, though Timothy can correct me if there is more to do. > Task 1.6: Top level modules and pad rings. The former are there but need > a careful look-over, the pad rings are still todo, right? > > Task 2.1: Design IO interfaces for HQ. There was some discussion about > this, and an interface for the XP10 side of the bridge is there, but > I'm unsure how far along HQ is at this point. This also relates to Task > 2.2: Insert HQ into the XP10. Update? > > Cheers, > > Lourens > > ------------------------------------------------------------------------ > > _______________________________________________ > Open-graphics mailing list > [email protected] > http://lists.duskglow.com/mailman/listinfo/open-graphics > List service provided by Duskglow Consulting, LLC (www.duskglow.com) _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
