On 2008-01-03, Timothy Normand Miller wrote:
> > Task 2.1: Design IO interfaces for HQ. There was some discussion about
> > this, and an interface for the XP10 side of the bridge is there, but
> > I'm unsure how far along HQ is at this point. This also relates to Task
> > 2.2: Insert HQ into the XP10. Update?
>
> HQ itself may be far enough along. It's just a variable we can
> eliminate for a first step. Once we have other stuff figured out, we
> can insert that.
I agree.
One thing I'd like to add is the rot instruction you suggested off-list.
Looking at drivers/hqlib/mulu.asm, it is clear that we save one
instruction in that loop. Not that we necessarily need multiplication,
but there may be other cases where we need to iterate from LSb to MSb.
I'll make room for the new instruction by using the same ALU operand
code for all three shift operations, move y-reg bits to the lower end
of y-immediates, and use the second and third highest immediate bit to
select the mode of the shifter:
16 | 15 14,13 4 0
mode | op | imm? | z-reg | x-reg |sign shift-mode y-reg
|<--------- y-imm ---------->
I consider using the attached rot/shift module. I'm not sure if this is
a good idea, but I force the synthesizer to make it O(log(N)) depth.
The three operations are combined to allow sharing the most expensive
part. Should I add the full license text and put it in rtl/lib?
Otherwise, I'll insert it in oga1hq.v.
module rot_shift_32(
input [1:0] mode,
input [31:0] factor,
input [5:0] expt,
output [31:0] result
);
parameter MODE_ROT = 0;
parameter MODE_LSL = 2;
parameter MODE_ASL = 3;
wire[63:0] z4 = {{32{mode[0] & expt[5] & factor[31]}}, factor};
wire[63:0] z3 = expt[4]? z4 << 16 : z4;
wire[63:0] z2 = expt[3]? z3 << 8 : z3;
wire[63:0] z1 = expt[2]? z2 << 4 : z2;
wire[63:0] z0 = expt[1]? z1 << 2 : z1;
wire[63:0] z = expt[0]? z0 << 1 : z0;
assign result =
(z[31: 0] & {32{!mode[1] || !expt[5]}})
| (z[63:32] & {32{!mode[1] || expt[5]}});
endmodule
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