On 1/3/08, Lourens Veen <[EMAIL PROTECTED]> wrote: > I've updated the status of a number of VGA Code Sprint tasks on the > wiki. For some of them I don't know their current status though, so if > anyone can enlighten me as to the following... > > Task 1.4: Design logic for the primary FPGA to process "engine" register > accesses. For configuration of the memory controllers and video > controller and so on. Is this built into the bridge? Or is it still to > be done?
Those exist already (in principle) for both chips. > > Task 1.6: Top level modules and pad rings. The former are there but need > a careful look-over, the pad rings are still todo, right? Top levels are basically done. The pad rings are config files that we'll have to get at least partials from Howard. > Task 2.1: Design IO interfaces for HQ. There was some discussion about > this, and an interface for the XP10 side of the bridge is there, but > I'm unsure how far along HQ is at this point. This also relates to Task > 2.2: Insert HQ into the XP10. Update? HQ itself may be far enough along. It's just a variable we can eliminate for a first step. Once we have other stuff figured out, we can insert that. > Cheers, > > Lourens > > _______________________________________________ > Open-graphics mailing list > [email protected] > http://lists.duskglow.com/mailman/listinfo/open-graphics > List service provided by Duskglow Consulting, LLC (www.duskglow.com) > > -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
