On 2008-08-01, Timothy Normand Miller wrote:
> Here's what the access target looks like now:
>
> parameter TARGET_CFG=0;
> parameter TARGET_ENG=1;
> parameter TARGET_MEM=2;
> parameter TARGET_VMEM=3;
> parameter TARGET_IO=4;
> parameter TARGET_PROM=5;
>
> access_target[4:1] is pushed into the command fifo, so flags[2] refers
> to VGA memory (A0000 to BFFFF), and flags[3] is I/O space. That
> target won't be understood by the S3, so we have to convert the
> accesses to MEM accesses, and it's HQ's responsibility to add an
> offset to the address.
If I understand this correctly, flags = 2^(target - 1) where target is
one of {TARGET_ENG, TARGET_MEM, TARGET_VMEM, TARGET_IO}? About the
translation, is the following correct?
TARGET_ENG -- MEM_SEND_ADDR_ENG without offset
TARGET_MEM -- MEM_SEND_ADDR_MEM without offset
TARGET_VMEM -- MEM_SEND_ADDR_MEM with offset 0xa0000
TARGET_IO -- HQ internal
Assuming it is, I made the following sketch of the poll_pci() function
(the stub from your original "VGA text mode C version" post). That
should nail down any misunderstanding I have about the bus protocol.
void poll_pci()
{
while (read_io(PCI_T_CMD_COUNT)) {
uint32_t addr, info, target;
/* Get the target and address */
info = read_io(PCI_T_CMD_INFO);
assert((info & PCI_TCINFO_TYPE_MASK) == PCI_TCINFO_TYPE_ADDR);
target = info & 15;
addr = read_io(PCI_T_CMD_DATA);
switch (target) {
case 1: /* engine */
write_io(MEM_SEND_ADDR_ENG, addr);
break;
case 2: /* memory */
write_io(MEM_SEND_ADDR_MEM, addr);
break;
case 4: /* video memory */
write_io(MEM_SEND_ADDR_MEM, addr + 0xa0000);
break;
case 8: /* IO */
handle_io(addr); /* TODO */
return;
}
while (read_io(PCI_T_CMD_COUNT) == 0);
info = read_io(PCI_T_CMD_INFO);
switch ((info & PCI_TCINFO_TYPE_MASK)) {
case PCI_TCINFO_TYPE_WDATA:
for (;;) {
uint32_t data = read_io(PCI_T_CMD_DATA);
uint32_t enables = info & 15;
write_io(MEM_SEND_DATA_0000 + enables, data);
if (!read_io(PCI_T_CMD_COUNT))
/* CHECKME: Is it possible to know if we should have
* waited for more data? */
break;
info = read_io(PCI_T_CMD_INFO);
}
break;
case PCI_TCINFO_TYPE_RCOUNT: {
uint32_t count, data;
count = read_io(PCI_T_CMD_DATA);
write_io(MEM_SEND_READ_COUNT, count);
while (count) {
while (!read_io(MEM_READQ_AVAIL));
data = read_io(MEM_READQ_DATA);
write_io(PCI_TR_DATA, data);
}
break;
}
default:
assert(!"The sky is pink.");
}
}
}
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