I'm working on a double modular redundancy "scheme" for unreliable
silicon that's wires up processor pipeline stages in similar spirit to
this diagram:
www.cse.ohio-state.edu/~millerti/in-order.pdf
I think it would be trivial to apply this to our own HQ, and as a
result have a legitimate reason to mention the OGP in a conference
paper. :)
All we need to do is hack the top level of HQ and drop it into some
test environment where it ran some code in an infinite loop, and we
would have some other block in the stimulus that would inject errors
into the pipeline. We could then collect statistics regarding its
ability to detect particle strike ("soft") errors. Then doing a
gate-level simulation, we could also simulate the occurrence of timing
errors.
Anyone interested in working on this with me?
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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