Just a note that we think we may have figured out what was going wrong. We've not completed the simulations to be sure. Anyhow, there's a cycle when PCI deasserts FRAME and IRDY, and we've deasserted TRDY. We're not sure if it's our fault or the host, but since this cycle is the end of the read transaction, we should probably stop driving the bus. We were still driving it for that cycle. My fix should eliminate the contention.
How Howard found it was interesting. I think it was AD19. It gets the input register clock from one bank of logic in the FPGA and the output register clock from another bank. This resulted in odd timing skews. If we add additional load to that signal on the bus, the data corruption goes away. Remove the load, and things break. I'm not sure how Howard got from there to figuring out what simulation to run, but he found the contention, and I modified the PCI target as described above. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
