I'd noticed that you've specified a fairly general-purpose processor
logic core in your design, omitting a multiplier from this for now.
Have you considered designs exposing multiple programmable processors,
or do you think this would be feasible for an initial (or perhaps later)
design?

There seems to be a fair amount of interest in using commodity hardware
for solving highly parallel problems, apparently including an earlier
post on this list, and since graphics seems to consistently fall into
this class, it seems natural to wonder how general the design could be.

The question is mostly motivated by working on some fairly parallel
problems for a little while; I've put together a summary of some
relevant ideas below, but it is a very general and non-technical draft,
and I suspect that others will have better, more complete ideas than
these.

http://auricle.dyndns.org/agc.html




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