2010/9/15 David Hilvert <[email protected]> > I'd noticed that you've specified a fairly general-purpose processor > logic core in your design, omitting a multiplier from this for now. > Have you considered designs exposing multiple programmable processors, > or do you think this would be feasible for an initial (or perhaps later) > design? >
That processor(HQ) is currently used to emulate VGA and also to do the DMA transfer, toward the graphics pipeline(OGA1). It reside in the chip doing the PCI bridge function. There's a second iteration of the architecture(OGA2) that has been partially specified. It's a work in progress, but it a model with programmable shader. It will support float and integer operation. > There seems to be a fair amount of interest in using commodity hardware > for solving highly parallel problems, apparently including an earlier > post on this list, and since graphics seems to consistently fall into > this class, it seems natural to wonder how general the design could be. > > The question is mostly motivated by working on some fairly parallel > problems for a little while; I've put together a summary of some > relevant ideas below, but it is a very general and non-technical draft, > and I suspect that others will have better, more complete ideas than > these. > > http://auricle.dyndns.org/agc.html > I'll look more to that link later and I'll try to give you a more complete answer. But from what I can see in that link a few of those idea are already present in modern processor. There also a chip from Actel(Coldfusion) that could be of interest if you want to do some kind of adaptive computing. That chip is an ARM cpu with a configurable analog front-end and FPGA logic cell.
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