Even if the HQ core or even HQ firmware does not do any bus
mastering, it might still be possible with the card.
But I fear that someone asking the question might have misunderstood
the purpose of the board. The Lattice chip is an FPGA and thus
reprogrammable. PCI bus master or not is not really a property of the
physical hardware.
As far as 2 signals (REQ and GNT) are connected to the Lattice FPGA, it
*is* the property of the physical hardware. I've checked the schematics
(10/15/07) and the card is bus master capable according to it. The
actual bus master functionality has to be programmed into the Lattice FPGA.
Daniel
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