The bus master logic is missing from the XP10.

I designed a simulation-only master as a test harness for the target.
My plan was to modify it to be more amenable to being controlled by HQ
and rewriting it to be synthesizable, but I never had the time.

Besides that, one of the challenges is that the master and target need
to share signals, which complicates things quite a lot.  All out-going
signals are registered meaning they have to be multiplexed before the
IOB registers, and this complicates the designs.  Also, a heck of a
lot of tricks will have to be played to make that meet timing.

OGD1's PCB is also wired to support 64-bit PCI, although the current
controller doesn't support it.

Before someone suggests the OpenCores PCI controller, let me lay this
one to rest.  First, wishbone is a poor interface, requiring very long
combinatorial paths, two-cycle transactions, or extra cycles at the
beginning and ends of bursts.  Our controller (and what we call the
"fifo protocol") doesn't have any of these problems.  Secondly, the
OpenCores controller isn't very well optimized and would never be able
to run at 66MHz, while ours can.


On Sat, Oct 2, 2010 at 5:12 PM, Peter Stuge <[email protected]> wrote:
> "Ing. Daniel Rozsnyó" wrote:
>>> PCI bus master or not is not really a property of the physical hardware.
>>
>> As far as 2 signals (REQ and GNT) are connected to the Lattice FPGA, it
>> *is* the property of the physical hardware.
>
> Excellent point! :)
>
>
>> I've checked the schematics (10/15/07) and the card is bus master
>> capable according to it. The actual bus master functionality has to
>> be programmed into the Lattice FPGA.
>
> Well put.
>
>
> //Peter
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-- 
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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